IBM has introduced a novel chip design that could potentially pack 100 billion transistors onto a surface no larger than a human fingernail. While current industry standards hover around two nanometres, this new technology reaches roughly 0.7nm, marking a significant step below the 1nm threshold. Although mass production remains years away, prototype testing indicates a 50% performance improvement and 70% greater energy efficiency compared to IBM’s existing 2nm chips.
Jay Gambetta, director of IBM Research, described the NanoStack architecture as a pivotal advancement in hardware engineering. By layering transistors vertically, IBM aims to overcome the physical limitations of horizontal scaling. Surrey University computer scientist Professor Alan Woodward likened the approach to building a 100-story skyscraper, noting that it appears significantly more ambitious than the 3D stacking efforts currently pursued by competitors like Samsung and Intel.
Technical hurdles remain, particularly regarding heat dissipation and the potential for electrical leakage when layers are extremely thin. Despite these challenges, the development represents a serious attempt to push past the boundaries of Moore’s Law, which suggests that the number of transistors on a chip doubles approximately every two years. This shift toward 3D chip design is essential for maintaining progress in the computing power required for modern data centers and the growing artificial intelligence sector.
